Silicon interposer explained
A silicon interposer is a thin slab of silicon that sits under a processor die and its high-bandwidth memory (HBM) stacks. It carries the dense die-to-die wiring, and through-silicon vias (TSVs) pass power, ground and I/O down to the package substrate. In TSMC's CoWoS flow, chips are bonded to an interposer wafer, and that assembly is then bonded to an organic substrate.
A finished AI accelerator wafer is still not a product you can ship. The logic die has to be joined to its memory on an interposer first. That work belongs to the back end of the supply chain, and in late 2026 the back end is where supply runs out. On TSMC's October 15, 2026 earnings call, CEO C.C. Wei said that "the demand actually is still far above our capability today to supply" and that "we have a little bit shortage on the back end," according to a third-party transcript published by Equibles. For operators buying accelerators and for investors deciding where capex earns a return, the interposer and the bonding steps around it now matter as much as wafer starts.
A circuit board made of silicon
Semiconductor Engineering describes interposers as "effectively platforms on which multiple components can be assembled" and compares them to "a micro-sized PCB." They "typically handle dense interconnects while passing I/Os, power, and ground to the package substrate below." A GPU sits next to several HBM stacks, and the thousands of short, fine-pitch connections between them run through the interposer instead of the coarser organic substrate.
The trade-off is that a silicon interposer is made like a wafer, not like a board. The same Semiconductor Engineering piece notes that silicon interposers need backside grinding to expose the TSVs, a step organic versions don't require. That extra processing, plus the cost of the silicon itself, explains why the 2.5D approach has stayed at the top of the market. An earlier Semiconductor Engineering analysis from 2018 described interposer cost as "relatively high, which limits 2.5D to high-end applications." AI accelerators are about as high-end as volume chips get, so they absorb that cost.
Three ways to connect chiplets
Package designers have three main options. Each one puts a different amount of silicon into the package:
| Approach | How it works | Trade-off |
|---|---|---|
| Full silicon interposer (for example, TSMC CoWoS) | All dies sit on one silicon slab, with TSVs down to the substrate | Densest wiring. Costly wafer-style processing, and large sizes need reticle stitching |
| Organic interposer | Redistribution wiring in organic material, built on panels | "Less expensive both in materials and fabrication," per Semiconductor Engineering, but gives up some electrical performance |
| Embedded silicon bridge (for example, Intel EMIB) | Small bridge dies embedded in the substrate or an organic interposer, placed only where dense links are needed | Uses less silicon, but assembly yield has slowed the cost benefit |
Intel's description of EMIB lays out the difference plainly: "Instead of using a large silicon interposer typically found in other approaches, EMIB uses a very small bridge die with multiple routing layers." Intel calls it the industry's first 2.5D embedded bridge solution. Semiconductor Engineering's 2025 coverage says bridges "provide dense interconnect between chips or chiplets, embedded in an organic interposer or substrate," but adds that "assembly-yield issues, however, have delayed the cost advantage that bridges eventually promise." Intel's newer EMIB-T variant adds channels through the bridge "to deliver power directly to the chips," according to an Intel release edited by StorageNewsletter.
The reticle problem
Lithography tools expose a limited area at a time. The 2018 Semiconductor Engineering piece put the maximum die size at 30mm x 30mm. Interposers larger than one reticle field have to be stitched together from several exposures, and Semiconductor Engineering reported in 2025 that Lightmatter is working on interposers eight reticles in size.
Accelerator vendors keep pushing past that limit because each generation adds more compute and more HBM. On the October call, Wei said TSMC is "in the real world production of 5x reticle size" and is "working on the 9x reticle size and moving into the 14x reticle size," per the Equibles transcript. He also said "the CoWoS is still the number one choice for our customers." Intel, for its bridge-based packages, says it is scaling to "8x the industry standard today, and over 12x by 2028."
Package size has a capacity cost. Packaging capacity is quoted in wafers per month, and a round 300mm wafer holds fewer large interposers than small ones. When interposer area grows, each accelerator uses more of a packaging line's wafer output. A rising wafers-per-month figure can therefore overstate how many more finished accelerators the industry can ship.
Map the steps before you map the suppliers
"CoWoS" is a sequence of separate operations, and they don't all happen at the same company or in the same country. TrendForce, citing ETNews, lays out the split:
| Step | What happens | Who does it |
|---|---|---|
| Interposer wafer fabrication | Wiring layers and TSVs are built on a silicon wafer, which is then thinned to expose the vias | TSMC. GlobalFoundries is to add US supply for CoWoS from 1H 2028 |
| CoW (chip-on-wafer) | Logic and HBM dies are bonded onto the interposer wafer | Mainly TSMC, with more now reportedly outsourced to OSATs |
| WoS (wafer-on-substrate) | The interposer assembly is bonded to the organic package substrate | Long outsourced: ASE, Amkor and SPIL make WoS under TSMC licenses |
| Test | The finished package is tested before shipment | TSMC and OSATs. TSMC's Arizona framework with Amkor covers packaging and test |
TrendForce describes CoW as "a key step in its CoWoS packaging technology." For years TSMC kept CoW in-house and outsourced mainly WoS. Moving CoW to OSATs is a sign that TSMC's own back-end capacity can't keep pace. For a buyer, it also means more companies in the qualification chain for one part number.
Why packaging, not wafer starts, sets the ceiling
The capacity numbers come from analyst and press estimates, not TSMC disclosures, and they should be read that way. TrendForce's August 2026 report puts TSMC's CoWoS capacity at about 70,000 wafers a month in 2025, rising to 130,000-140,000 by the end of 2026. A June TrendForce report citing Economic Daily News gives 120,000-140,000 for 2026 and adds 50,000-60,000 wafers a month of new OSAT capacity. On that basis the industry total "could approach 200,000 wafers per month."
Even after roughly doubling, supply is still short. The same June report says institutional investors expect the CoWoS supply-demand gap to narrow "from around 20% currently to about 10%" by the end of 2026. TrendForce expects the 2.5D shortage "to begin moderating by 2027" and cites TSMC's plan to expand CoWoS capacity by more than 60% by 2027.
Capacity is also concentrated. TrendForce, citing Mydrivers, reports that NVIDIA reserved about 800,000-850,000 wafers of 2026 CoWoS capacity, more than half the total. A smaller ASIC program or a second-tier accelerator buyer competes for what's left.
US capacity, one step at a time
The US starts from a low base. CSIS wrote in 2023 that "the United States' share of global packaging capacity stands at 3 percent," that about 81% of global assembly, test and packaging capacity is in Asia, and that "other than Intel, no semiconductor firms operate large-scale advanced packaging facilities in the United States." InBusiness Phoenix cites a 2024 SIA/BCG report giving the same 3% for 2022. The Register notes that Blackwell GPUs made in Arizona still had to be shipped to Taiwan for final assembly.
Intel, Rio Rancho, New Mexico. This is the only site on the list running today. It does EMIB and Foveros packaging. Intel's release says the site has 2,700 employees and 500 suppliers. It runs Intel's bridge approach, not CoWoS.
GlobalFoundries, Malta, New York. The Register reports a $2 billion deal under which GF will produce silicon interposers for TSMC's CoWoS at Malta. The deal runs five years with an option to extend, and volume production isn't expected before the first half of 2028. The Taipei Times also reports the 1H 2028 ramp. In an October 14, 2026 SEC filing, GF said it will reallocate $955 million of its CHIPS Act award to silicon photonics, SiGe and advanced packaging at Malta and Burlington, Vermont. Wei described the deal as "part of our overall strategy in the back-end supply."
Amkor, Peoria, Arizona. Amkor announced a CHIPS award of up to $407 million on December 20, 2024, for an initial facility of about $2 billion. Manufacturing Dive later reported a $7 billion, two-phase plan with 750,000 square feet of cleanroom. Construction is due to finish in mid-2027 and production to start in early 2028, with Apple as the "first and largest customer." AZ Big Media reports planned investment has grown to about $12 billion. Phase 2 adds 60,000 square meters of cleanroom to Phase 1's 33,000 on a 170-acre campus with more than 3,500 employees, and Phase 2 construction runs from late 2027 to the end of 2029. AZ Big Media says the expansion is backed by an NVIDIA prepayment under a multiyear partnership. Separately, InBusiness Phoenix reports NVIDIA struck a $1.5 billion multi-year deal with Amkor in July 2026. TrendForce reports a 10-year framework under which "TSMC will procure advanced packaging and testing services from Amkor" in Arizona.
TSMC, Arizona. TrendForce, citing ESM China, says TSMC plans its first Arizona advanced packaging facility "by 2029, with CoWoS and 3D-IC capacity." InBusiness Phoenix reports that TSMC says construction began in early 2026 and that its plan includes two advanced packaging facilities.
Taken together, domestic CoWoS-class interposer supply, chip-on-wafer bonding and substrate attach are all targets for 2028 and 2029. None of them is running at volume now.
What buyers and investors should do with this
If you buy accelerators or design custom silicon, treat US-sourced 2.5D packaging as a 2028-and-later qualification plan, not a 2027 supply lever. Ask your suppliers which steps are dual-sourced: interposer fabrication, CoW, WoS and test each carry their own risk. A package that's "packaged by an OSAT" may still depend on a single interposer source. Assume allocation will favor the largest customers while the reported gap persists. Plan volumes against committed capacity, not against the industry's wafers-per-month headline.
For investors, the spending has spread well beyond wafer fabs. It is going into interposer production at a foundry outside TSMC, CoW bonding moving to OSATs, substrate attach and test, and research on panel-based formats. Read the dated facility plans as targets. Amkor's phase timelines, GF's 1H 2028 ramp and TSMC's 2029 packaging plant are construction and ramp schedules, not output.
Where the bottleneck goes next
Every alternative on the roadmap tries to use less full-wafer silicon. Organic interposers swap wafers for panels. Bridges like EMIB put silicon only where the links need it. TSMC set up a CoPoS (chip-on-panel-on-substrate) R&D line at VisEra in 2025, according to TrendForce citing Commercial Times, and Wei said on the October call that TSMC is "also working on the CoPoS part." Each approach could ease demand on interposer wafers. Each also brings its own yield curve and its own suppliers, as the bridge experience shows. If TrendForce's forecast holds and the 2.5D shortage begins moderating in 2027, the next thing to watch is whether substrates, panels or test capacity become the constraint once interposers no longer are.
Related reading
Sources
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What's Next for 2.5D Packaging? (Semiconductor Engineering, Dec 18, 2025)
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Bridges Vs. Interposers (Semiconductor Engineering, Jul 12, 2018)
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Intel EMIB technology explained (Intel)
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Intel's US Advanced Packaging Enables Next-Generation AI Semiconductors (StorageNewsletter, Aug 21, 2026)
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Taiwan Semiconductor (TSM) Q3 2026 Earnings Call Transcript (Equibles)
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TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026 (TrendForce, Jun 15, 2026)
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TSMC Reportedly Expands Outsourcing of Key CoWoS Front-End Step to OSATs (TrendForce, Aug 5, 2026)
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TSMC, Amkor Sign 10-Year Arizona Advanced Packaging Pact (TrendForce, Jun 17, 2026)
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TSMC taps GlobalFoundries to bolster US silicon interposer production in $2B deal (The Register, Oct 8, 2026)
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GlobalFoundries rallies after US$2bn TSMC deal (Taipei Times, Oct 10, 2026)
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GlobalFoundries Form 6-K press release (Oct 14, 2026)
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Biden-Harris Administration Announces CHIPS Incentives Award with Amkor Technology (Amkor, Dec 20, 2024)
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Amkor Arizona $7 billion semiconductor campus (Manufacturing Dive, Oct 8, 2025)
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Amkor increases investment in new Arizona facility to $12 billion (AZ Big Media, Sep 28, 2026)
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Some Assembly Required: Arizona Builds the Last Step in Chipmaking (InBusiness Phoenix, Oct 2026)
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Advanced Packaging and the Future of Moore's Law (CSIS, Jun 26, 2023)