When TSMC's board met on May 12, 2026 and signed off on another US$31.28 billion in capital appropriations alongside a separate authorization of up to US$20 billion to capitalize TSMC Arizona, the wire copy almost wrote itself: a record budget, a giant Phoenix injection, and a tidy implication that the U.S. is finally pulling a meaningful share of leading-edge spending off the island. Some outlets, including the Taipei Times, printed the headline figure as $31.38 billion — a transcription wobble worth flagging before any reader does capex arithmetic on it.
The arithmetic is the problem. Read as a clean partition — $20B to Arizona, $11B-ish staying in Taiwan and Japan — the numbers tell a story about decoupling that the underlying disclosures do not support. They are appropriations stacked on prior appropriations, not a full-year capex pie. And the binding constraint on how quickly leading-edge silicon can actually leave Taiwan is not wafer fabs. It is the packaging loop sitting behind every AI accelerator shipping today.
What the $31.28B actually is
Appropriations are spending permissions, not cash outlays. TSMC's board has been issuing them in tranches throughout 2026. In February 2026 the board signed off on a record ~US$44.96 billion tranche for production expansion. The May 12 action adds another $31.28 billion on top of that, plus the separate Arizona capitalization. Stacked, these approvals comfortably exceed full-year 2026 capex guidance, which TSMC has held to US$52–56 billion and has signaled is trending toward the upper end.
The implication for the U.S.-vs-Asia framing is direct. Comparing the $31.28B May headline against the $20B Arizona injection as if they jointly equal 2026 cash capex understates the Taiwan and packaging spend pool by tens of billions. The relevant denominator is the $52–56B guidance, and TSMC has been explicit about the mix inside it: roughly 70–80% advanced process (N3, N2, A16), 10–20% advanced packaging and mask making, and about 10% specialty nodes. Arizona is a line item inside that distribution, not a rival to it.
What the $20 billion to Arizona buys
The Arizona capital injection is a parent-to-subsidiary transfer into the entity running Fab 21 in Phoenix. Trade press coverage ties the money to three specific commitments: accelerating Fab 21 Phase 2, where TSMC told investors in January that N3 volume production will start in the second half of 2027 rather than the original 2028 date; tooling preparation for N2 at the same site; and the long-running site work behind Phase 3 and the broader $165 billion Arizona commitment.
The execution risks have not changed because the appropriation got bigger. Water availability, construction and operator labor, and visa pathways for specialist Taiwanese engineers remain the same friction points that have shadowed Fab 21 since groundbreaking. A capital injection clears a balance-sheet constraint at the subsidiary; it does not clear a labor market.
What the rest of the spend actually buys in Taiwan
Strip out Arizona and the residual 2026 spending pool is overwhelmingly oriented toward two things: ramping 2nm and expanding advanced packaging in Taiwan.
On the wafer side, N2 entered volume production in Q4 2025. Five 2nm fabs — two in Hsinchu and three in Kaohsiung — are scheduled to ramp through 2026, and TSMC has guided to a 70% compound growth rate on 2nm capacity from 2026 through 2028. Analysis of the February tranche read it as a deliberate pull-forward of 2nm tool-in spending; the May tranche extends that posture rather than reversing it.
On the packaging side, the story is AP6 in Zhunan, AP7 in Chiayi (slated to become the company's largest advanced packaging hub), and AP8 in Tainan. CoWoS capacity is the gating resource for almost every leading-edge AI accelerator, and TSMC is targeting roughly 130,000 CoWoS wafers per month by late 2026 — close to a quadrupling of late-2024 output. NVIDIA alone is expected to absorb more than half of end-2026 capacity.
The packaging ceiling on decoupling
This is where the decoupling narrative bumps into physics and floor plans. Even when a wafer is fabricated in Phoenix, it still loops back through Taiwan for CoWoS-L — the LSI-bridge variant TSMC has positioned as the leading interconnect for greater-than-two-reticle GPU and HBM packages. The next-generation panel-level packaging variant, CoPoS, is also Taiwan-anchored: TrendForce reports the CoPoS pilot line is targeted for June 2026 completion, with volume ramp not expected until 2028–29.
Arizona's announced advanced packaging facilities exist on paper, but they are years away from materially relieving the Taiwan loop. Until then, every accelerator that benefits from the Arizona-made die still depends on Zhunan, Chiayi, and Tainan for the package that ties it to high-bandwidth memory. The wafer is American; the system-in-package is not.
Japan: the slack leg of the diversification story
The Kumamoto story has gone in the opposite direction from Phoenix. JASM Phase 2, the second Japanese fab, has been pausing construction since late 2025. TSMC has removed heavy equipment from the site and told suppliers it will not need new fab tools in Japan during 2026. Mass production at JASM 2 has reportedly slipped roughly 18 months to 2029, with a potential node shift from the originally planned 6/7nm to 4nm under review.
That matters for how the geopolitical story reads. Japan was supposed to be the second leg of the diversification stool, a politically frictionless partner location for mature and trailing-edge nodes that would absorb meaningful capacity. Instead, the Japan leg is shrinking in 2026 while Arizona is the one being accelerated. The diversification headline survives only because Phoenix is doing the heavy lifting alone.
The CHIPS Act sized the wrong layer
The structural reason packaging is the ceiling is policy as much as geography. CHIPS Act subsidies were sized around wafer fab construction — the capital-intensive front end. Outsourced semiconductor assembly and test, and the advanced packaging adjacent to it, were never the focus of the subsidy architecture. U.S. policy leverage over the packaging layer is therefore structurally limited until AP-class facilities exist on American soil, and those facilities currently exist mostly as line items in TSMC's longer-dated Arizona roadmap.
That gap is the practical ceiling on what a $20 billion Arizona injection can buy in terms of supply-chain resilience. It accelerates wafer output. It does not bring forward the date at which an AI accelerator can be fabricated, packaged, and tested without ever touching Taiwan.
What operators and investors should watch
Four near-term signals will matter more than the next round of headline appropriations. First, Q2 earnings call commentary on the packaging mix inside 2026 capex — anything that shifts the 10–20% advanced packaging allocation upward implies the CoWoS ceiling is binding harder than disclosed. Second, Arizona Phase 2 tool-in timing: the H2 2027 N3 production date is the metric, not the appropriation amount. Third, the next status update from JASM on Kumamoto Phase 2; a confirmed pivot to 4nm would reshape the trailing-edge map. Fourth, whether TSMC raises the $52–56B 2026 capex band again. Two appropriation tranches in three months already imply pressure on the upper bound.
The cleaner read on May 12 is this: TSMC is spending aggressively on both sides of the Pacific, the Arizona injection is real and meaningful for U.S. wafer capacity, and the decoupling story still has a hard ceiling — set not in Phoenix or Hsinchu, but in the packaging buildings outside Chiayi.
Related reading
Sources
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TSMC approves US$31.28 billion capital budget for expansion — Focus Taiwan
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TSMC approves US$31.38 billion capital budget for expansion — Taipei Times
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TSMC allocates $20 billion to Arizona expansion — Tom's Hardware
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TSMC's board approves $45 billion spending package on new fabs — Tom's Hardware
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TSMC announces 2026 capex spend of $56bn — Data Center Dynamics
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TSMC's second Japanese fab reportedly delayed, mass production pushed to 2029 — Tom's Hardware
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TSMC pauses work on second Kumamoto wafer fab — DIGITIMES
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TSMC Advances Panel-Level Packaging, CoPoS Pilot Line Reportedly Set for June Completion — TrendForce
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TSMC officially begins 2nm chip volume production in Q4 2025 — Taipei Times
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Why is TSMC spending $45bn so early? — DIGITIMES