Extraction Challenges of CFET and Backside Power Delivery
Semiconductor Engineering has published analysis on the parasitic extraction challenges associated with Complementary FET (CFET) transistor architectures and backside power delivery networks, two of the most significant structural changes in sub-2nm semiconductor process nodes. The piece addresses workflow setup, interface resistance modeling, and RLCK (resistance, inductance, capacitance, and coupling) extraction as critical enablers for next-generation device reliability and power efficiency. These challenges sit at the intersection of process development and physical design verification.