On Aug. 7, 2026, SK hynix's board approved 54.3 trillion won — roughly $38 billion — for two new fabs: Yongin Y2, a 35.2 trillion won DRAM plant including HBM on a 1.13 million m² site in Gyeonggi Province, and Cheongju M17, a 19.1 trillion won NAND plant on about 680,000 m² in North Chungcheong. It is the largest single capacity commitment made during this memory cycle, and it is the clearest answer any supplier has given to the question American manufacturers have been asking since DRAM contract prices nearly doubled in a single quarter: where is the new supply coming from?
The answer is Korea. Not Texas, not upstate New York, not Arizona. The most consequential capacity decision of the shortage was sited inside a domestic cluster that will absorb 600 trillion won of investment before it is finished.
The frame, stated precisely: wafers in Korea, back-end in America
It would be wrong to say SK hynix skipped the U.S. incentive zone. The company is building a $3.87 billion advanced packaging and R&D facility in West Lafayette, Indiana, at Purdue Research Park, backed by up to $458 million in CHIPS direct funding, with mass production expected in the second half of 2028 and roughly 1,000 facility jobs. What the company did not put in the United States is wafer capacity. HBM stacking and back-end packaging go to Indiana; the DRAM and NAND fabs go into the Korean cluster.
That split is the actual story, and it is more interesting than a subsidy-shopping narrative. Yongin Y2 is step two of a plan disclosed in June 2026: 600 trillion won for a 4.2 million m² Yongin cluster in the Wonsam district and 100 trillion won for Cheongju, with all four Yongin fabs now targeted for completion by 2033 — pulled forward from an original 2045 horizon. Cluster density, shared utilities, and tool-in speed beat incentive capture when the binding constraint is how fast you can qualify a new node. A company official framed the logic directly: "In the AI era, technological competitiveness alone is not enough. The ability to supply customers with the products they need when they need them is itself a source of competitiveness." SK hynix is separately weighing a sale of its Chongqing, China plant, which points the same direction — consolidation toward the home cluster.
The timeline should end any hope of near-term relief
Read the schedule before you model 2027. Per SK hynix's own announcement, Y2 breaks ground in July 2027, with its first cleanroom completed in June 2029. M17 breaks ground in February 2027, cleanroom in December 2028. That is roughly three years from board resolution to a room that can hold tools — before qualification, before yield ramp, before a single qualified industrial part number ships.
The American side is no faster. Micron has raised its U.S. commitment to more than $250 billion through 2035 and poured first concrete at its Clay, N.Y. fab running 25%+ ahead of schedule — but New York DRAM output does not arrive until 2030. Idaho, with initial production expected mid-2027, is the only near-term U.S. bit source of consequence.
The operative sentence for planning purposes: nothing announced in 2026 ships meaningful wafer volume before 2028. Every procurement decision between now and then is a decision about how to ration existing bits.
Follow the cost into your P&L
The price record is unambiguous. TrendForce puts 1Q26 conventional DRAM contract prices up 93–98% QoQ, driving industry revenue to $97 billion, up 81% sequentially — Samsung at $37.32B (+93.4%), SK hynix at $27.98B (+62.5%), Micron at $21.75B (+81.6%). The 2Q26 forecast called for another 58–63% QoQ on DRAM and up to 75% on NAND.
Spot markets tell the same story at the component level: DDR4 8Gb mainstream ran $35.12 the week of June 3, 2026 and $35.90 the week of June 9, then set a record $41.10 the week of July 21. At the module level, a 64GB DDR5 RDIMM moved from roughly $255 in Q3 2025 to about $450 in Q4 2025 and crossed $900 in Q1 2026 — a tripling in three quarters on a part that sits in the BOM of every industrial server, edge-AI gateway, and machine-vision controller.
One number deserves a sourcing note, because it is circulating without one. The widely quoted "700%" figure traces to VersaLogic, an embedded-computing OEM, in January 2026, describing individual memory components running "up to 700% compared to historical pricing." It is a supplier's field observation on specific parts, not a spot index. Use it as a datapoint about the worst-case line items in an embedded BOM, not as a market-wide inflation rate.
The LTA split: hyperscalers capped their prices, you didn't
This is the least-covered and most economically important dynamic in the market. TrendForce forecasts server DRAM contract prices rising only 13–18% QoQ in 3Q26 — a dramatic deceleration from Q1's near-doubling. That deceleration is not evidence of loosening supply. It is the arithmetic of contracts: U.S. cloud service providers signed multi-year long-term agreements that restrict suppliers from raising their prices.
Suppliers still need the revenue. If the largest buyers are contractually capped, the residual increase lands on everyone outside those agreements — which is to say industrial OEMs, controls builders, automotive tier suppliers, and anyone whose annual memory spend is too small to command a multi-year commitment. VersaLogic reports Samsung seeking increases of up to 20% in 3Q26 contract pricing. A manufacturer reading "server DRAM up 13–18%" as a market-wide ceiling will underfund its Q4 material budget.
The structural point: in an allocation market, price discipline flows to scale. Being small is now a direct cost-of-goods penalty, not just a negotiating disadvantage.
What an allocation market does to production planning
Price is the visible symptom. The operational damage is in the terms. From VersaLogic's supply-chain briefs across January–August 2026:
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Lead times of 8 to 52 weeks depending on product, with 32–40+ weeks typical as of January.
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Memory purchased only against firm customer POs — suppliers are no longer buying to forecast, which kills the forecast-based buffer builds most operations teams rely on to absorb demand variability.
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Quote validity compressed to 72-hour windows. A quote you sat on over a weekend is dead.
Each of those breaks a different planning assumption. A 40-week lead time on a component means your 2027 build plan is being locked now, at prices you cannot hedge. The end of forecast-based buying means safety stock has to be bought with your own committed capital and your own PO risk, not the distributor's. And 72-hour quotes mean approval chains built for weekly purchasing cadences are structurally too slow — the sign-off latency itself is now a cost line.
The only genuine lever left is ordering earlier and firmer. That is a working-capital decision made under price uncertainty, and it belongs in front of a CFO, not buried in a purchasing workflow.
The redesign trap
The instinctive engineering response to a price spike is to respec down: pull the expensive DDR5 module, drop back to a cheaper legacy node, eat the performance loss. In this cycle that move runs directly into a wall.
DDR4 is the sharpest squeeze in the market, not the relief valve, because Samsung and SK hynix are winding down legacy lines to free capacity for HBM and advanced nodes. That is why DDR4 8Gb spot set a record in July. Tightness has already spilled into DDR3 as buyers downgrade, and DDR3/DDR3L are reaching end of life — forcing last-time-buy decisions on exactly the industrial and automotive designs least able to absorb a redesign.
So the escape route inverts. Respeccing backward moves you toward a supply base that is actively being dismantled and toward parts with a terminal purchase date. For any design with a multi-year production life, the defensible answer is usually to design forward to DDR5 despite the price, and to treat any remaining DDR3/DDR4 design as a last-time-buy problem with a hard quantity and a hard date attached. Run that math now: units per year × remaining program life × attrition, against a component that may have one buy window left.
The closing arithmetic
Three suppliers hold roughly 90% of DRAM revenue — Counterpoint's Q2 2026 figures put Samsung at 39%, SK hynix at 26%, and Micron at 25%. (The commonly repeated "95%+" concentration figure is stale.) Notably, SK hynix's share fell from 39% a year earlier even as its revenue rose 214% YoY — the market grew faster than it did.
The only genuinely new supply entrant is China's CXMT, now fourth at 7% share on 716% YoY revenue growth, with Nanya up 690%. CXMT's growth is real and it is the single most important variable in any 2028 supply model. It is also not, today, a qualified Tier-1 source for most industrial and automotive programs — qualification cycles, longevity commitments, and export-control exposure all sit between that 7% and a Western OEM's approved vendor list.
Meanwhile, total RDIMM bit supply is growing only 15–20% YoY, far behind server CPU growth, and TrendForce already treats a 2027 server DRAM shortage as a given rather than a risk.
Put the pieces together and the position of an industrial buyer is structural, not accidental. The incremental bit goes to HBM, because HBM earns more per wafer. The remaining conventional supply is price-capped for hyperscalers by contract, which pushes the residual increase onto everyone else. New wafer capacity — Korean or American — is a 2028-to-2030 event. Industrial customers are last in line by design.
A procurement checklist for the next four quarters
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Audit BOM memory exposure by program. Identify every design with DDR3, DDR3L, or DDR4 content and rank by remaining program life. These are your EOL liabilities.
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Pursue LTA-equivalent commitments. If you cannot sign a multi-year agreement alone, aggregate volume across programs, divisions, or contract manufacturers. Uncapped exposure is now the expensive default.
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Stage last-time-buys deliberately. Set quantities and dates against firm program forecasts rather than reacting to an EOL notice on a supplier's timetable.
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Compress approval latency to fit 72-hour quotes. Pre-authorize buyers to commit within defined price bands; the sign-off chain is now part of the cost.
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Model supply relief from 2028, not 2027. Y2's cleanroom lands in June 2029 and Micron's New York DRAM in 2030. Idaho in mid-2027 is the only near-term U.S. bit source, and it is not sized to fix this.
SK hynix put $38 billion behind the proposition that supply timing is itself a competitive weapon. It is — and for the next two years, it belongs to whoever locked in a contract, not to whoever needs the parts.
Related reading
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[TSMC Doubles Down on Arizona to $265B — Four More 2nm-and-Below Fabs, Bankrolled by a Record Quarter](/article/tsmc-arizona-265-billion-four-more-2nm-fabs-record-q2-2026)
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[Micron Just Pulled Its Clay Fab a Quarter Ahead — and Raised the U.S. Bet to $250B to Print 40% of Its DRAM at Home](/article/micron-clay-fab-ahead-of-schedule-250-billion-dram)
Sources
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SK hynix Invests 54 Trillion Won in Yongin Y2 and Cheongju M17 — SK hynix Newsroom
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SK hynix to invest W54tr in new Yongin, Cheongju fabs — The Korea Herald
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Rapid Contract Price Surge Drives 1Q26 DRAM Industry Up 81% QoQ — TrendForce
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DRAM prices predicted to jump 63% in Q2, NAND up to 75% — Tom's Hardware
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AI Demand Reshapes DRAM Rankings in Q2 2026 — Counterpoint Research
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Supply Chain Brief: Memory Market Conditions in 2026 — VersaLogic
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Memory Spot Price Update: DDR4 Tightness Spills Over to DDR3 — TrendForce
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Micron Raises U.S. Investment Target to $250B Through 2035 — TrendForce