Manufacturing Wire

Semiconductor Engineering reports that 3D multi-die packaging architectures are driving new IP requirements as vertical signal paths introduce complex parasitic interactions that are increasingly difficult to model and control. The shift toward stacked die configurations — including chiplets and heterogeneous integration — demands more sophisticated design verification and interface standardization. Existing IP blocks developed for planar designs are proving inadequate for the thermal, electrical, and mechanical demands of vertical interconnect stacks.

Semiconductor Engineering highlights the growing necessity of hardware security verification during pre-silicon design phases, arguing that increasing system complexity makes reactive or isolated security checks insufficient. The piece advocates for systematic security validation embedded earlier in the chip design process, before physical fabrication begins. This shift represents a methodological change in how semiconductor manufacturers approach security assurance across the development lifecycle.

SRAM is losing its ability to scale efficiently at advanced process nodes, creating a widening gap between processor compute throughput and available on-chip memory bandwidth — a phenomenon known as the memory wall. The article argues there are no near-term solutions ready to close this gap, forcing the semiconductor industry to reassess memory architecture across computing applications. This affects everything from edge inference hardware to industrial controllers that depend on SRAM-dense chips.

Semiconductor Engineering covers advances in parasitic extraction workflows for complementary field-effect transistors (CFETs) and buried power rails, two critical architectural features at leading-edge process nodes below 2nm. Accurate extraction of resistance, capacitance, and inductance at these geometries is essential for sign-off verification before tape-out. The piece addresses how EDA tooling must evolve to handle 3D device stacking and subsurface metallization layers that conventional extraction engines were not designed to characterize.

Engineering.com convened a panel of experts to examine post-processing requirements for metal additive manufacturing parts, covering mechanical, chemical, and electrochemical surface finishing methods. The discussion addresses the gap between as-built surface roughness from metal AM processes and the finish specifications required for functional end-use components. Key insights span process selection criteria, material compatibility, and the engineering tradeoffs involved in each finishing approach.

Magna International has introduced the DHD REX, a hybrid drive unit designed for electric vehicles featuring a multi-mode architecture. The system supports pure electric driving while offering an optional parallel hybrid mode to extend range capability. Magna positions the unit as a solution for OEMs looking to bridge full-EV range limitations without sacrificing drivability.

ABB has launched a SaaS deployment option for its Ability OPTIMAX 7.0 energy management and optimization platform, alongside updated advanced process control software. The new model allows industrial and energy operators to deploy, scale, and manage energy and process optimization tools across complex multi-site facilities without traditional on-premises installation overhead. This represents a shift in how enterprise-grade process optimization software is delivered to heavy industry.

ASRock Industrial has released the AI BOX-A395, a compact edge computing system built around the AMD Ryzen AI Max+ 395 processor with up to 128GB of LPDDR5x memory. The unit features 10GbE and USB4 connectivity, positioning it for deployment in industrial and edge AI inference applications. The form factor is designed for space-constrained environments typical of factory floor installations.

congatec has launched a partner program called aReady.YOURS targeting embedded systems development for regulated OEM markets. Kontron is the inaugural partner in the program, with the collaboration focused on North American and EMEA markets. The program appears designed to create a structured ecosystem around congatec's embedded computing modules for industrial and regulated applications.

LPDDR6 memory represents the next generation of low-power double data rate memory, delivering improved bandwidth efficiency, more predictable latency, and enhanced platform reliability compared to LPDDR5 and LPDDR5X. Scale AI has published technical analysis detailing the architectural changes driving these improvements, with particular focus on AI system workloads. The specification advances are targeted at edge AI deployments where power budgets and thermal constraints are tightly managed.

Semiconductor Engineering reports that thermal management has become the primary performance and reliability constraint in multi-die 3D integrated circuit packages. As chipmakers stack dies vertically to increase compute density, heat dissipation between tightly coupled silicon layers presents significant engineering challenges that affect both device performance and long-term reliability.

Semiconductor Engineering has published analysis on the parasitic extraction challenges associated with Complementary FET (CFET) transistor architectures and backside power delivery networks, two of the most significant structural changes in sub-2nm semiconductor process nodes. The piece addresses workflow setup, interface resistance modeling, and RLCK (resistance, inductance, capacitance, and coupling) extraction as critical enablers for next-generation device reliability and power efficiency. These challenges sit at the intersection of process development and physical design verification.

Semiconductor Engineering's March 25 blog review aggregates technical commentary across several engineering disciplines, including model-based systems engineering (MBSE) for multiphysics applications, UALink verification IP, electromagnetic simulation advances, and silicon-on-insulator (SOI) developments. The roundup also addresses the distinction between traceability and tracking in design workflows, as well as code migration strategies. These topics reflect ongoing challenges in semiconductor design methodology and verification.

Semiconductor Engineering published analysis on the critical engineering challenges involved in building AI chips, focusing on security architecture, software development workflows, and lifecycle management across the chip's operational lifespan. The piece addresses how AI chip designers must integrate security considerations from the earliest design stages rather than retrofitting them later. Lifecycle management encompasses everything from initial silicon validation through field deployment and eventual end-of-life handling.

TotalEnergies and Holcim have commissioned a 31 MW floating photovoltaic installation on a rehabilitated chalk quarry lake in Obourg, Belgium. The plant generates approximately 30 GWh per year of renewable electricity, which is directly self-consumed by Holcim's adjacent cement manufacturing operations. The project repurposes an existing industrial brownfield water body, avoiding competition for productive land.

Amyris has completed construction of a fourth production line at its precision fermentation facility in Barra Bonita, Brazil, expanding on three existing lines at the plant. The expansion is designed to increase output capacity for bio-based compounds produced through precision fermentation technology. The Emeryville, California-based company positions this as a response to growing demand for sustainable ingredients.

Data experts at Ford detail how AI agents are transforming manufacturing operations, from autonomous production oversight to predictive maintenance that has reduced unplanned downtime by up to 40%. AI-driven quality control is achieving 30-50% defect rate reductions through real-time machine vision and sensor fusion, while energy optimization tools are delivering 15-20% savings across plants.

While fewer than half of AI projects have moved past the pilot phase, experts say the real productivity breakthrough in manufacturing will come when AI systems are interconnected across departments. McKinsey describes the current state as a productivity paradox similar to the early PC era, where gains only materialized once systems were networked across organizations.

AT&T builds out ‘connected AI’ strategy for industrial edge

TCS launches Gemini experience centre in the US to accelerate AI powered manufacturing